RX63N Groups

• Execution Unit:
  • nteger operations, 5-stage execution pipeline
  • 32-bit single precision Floating Point Unit compliant to IEEE-754 specification
  
• 
  Digital Signal Processing:
  • 48-bit MAC, 80-bit RMPA, 32-bit Barrel Shifter
• 
  Register Set:
  • 9 X 32-bit Control Registers
  • 16 X 32-bit General Purpose Registers
  • 48-bit Accumulator Register
  
  
• Memory Protection Unit:
  • Eight programmable protection regions
  
  
• Interrupt Control Unit:
  • Configurable for Normal and Fast interrupt handling with option to dedicate up to four General Purpose registers for interrupt use
  
  
• On-chip Debug:
  • JTAG or 2-wire
  • High-speed trace (6-wire)
  
  

• Communication:
  • Ethernet MAC (RX63N only)
  　　> 10/100, full/half duplex
  　　> Supports Xmit and Rcv IEEE-802.3
  　　> 2KB SRAM buffers for xmit & recv w/DMA support
  　　> Supports MII and RMII to external PHY
  • USB Full Speed Host or Device
  　　> Up to 2 channels, either can be host or device
  　　> PHY included for both USB channels
  　　> OTG operation with external Vbus switch
  • 3 CAN Interface with 32 Mailboxes
  • 13 SCI, 4 I2C, 3 SPI, 32-bit external data bus
  
  
  
• Timers:
  • Specialized for motor control, plus standard timers
  
• 
  
• Data Movement:
  • 4 Programmable DMA channels
  • 85 DTC channels, linked-list control
  • External DMA controller can drive color TFT-LCD with up to WQVGA resolution
  
• 
  Analog:
  • 21 channel 12-bit ADC
  • 8 channel 10-bit ADC
  • 2 channel 10-bit DAC
  • Temperature Sensor